1. Field of the Invention
The present invention relates to an apparatus and a method of repairing memory cells for converting a higher density memory cell into a lower density memory cell to utilize it, and more particularly to a memory cell repairing apparatus and a method of repairing failed memory cells in case that a rule in failure is detected even though various types of failures are generated.
2. Description of the Prior Art
As integration density in semiconductor memory devices increases, the size of individual cells decreases. In contrast, a cell fabricating process becomes complex in order to obtain the corresponding capacitance irrespective of the smaller size, thus failure rate in cells increases. In case that the amount of failure rate exceeds that of the redundancy, a number of chips cannot be repaired. Accordingly, techniques for repairing normal memory cells other than the failed memory cells are required. For example, first, the technique for repairing memory cells in the range limited to single bit fail, word line fail, and column fail. Second, the technique for repairing memory cells by converting a high integrated circuit to a low integrated circuit.
In the second technique, for example, a 16M-memory device is converted to an 8M memory device, or a 8M memory device is converted to a 4M memory device. The conventional technique such as the second technique is used to repair memory cells selected from the entire memory cells by bonding residual address signals to the ground or power voltage when the failed memory chip is converted to a low integrated device. The second conventional memory cell repairing technique is disclosed in the Korean Patent Application No. 1996-47789 entitled xe2x80x9cMEANS FOR REPAIRING PARTIAL BLOCK OF MEMORY CELL AND METHOD OF REPAIRING THE PARTIAL BLOCK USING SAMExe2x80x9d filed Oct. 23, 1996 in the name of Samsung Electronics Co., Ltd. (hereinafter, referred to by reference 1), the Korean Patent Application No. 1999-51337 entitled xe2x80x9cSEMICONDUCTOR MEMORY APPARATUS AND METHOD OF REPAIRING THE APPARATUSxe2x80x9d filed Nov. 18, 1999 in the name of Samsung Electronics Co., Ltd. (hereinafter, referred to by reference 2), and the U.S. Pat. No. 5,905,683 entitled xe2x80x9cMETHOD AND STRUCTURE FOR RECOVERING SMALLER DENSITY MEMORIES FROM LARGER DENSITY MEMORIESxe2x80x9d, filed Sep. 29, 1997 in the name ST Microelectronics, INC. (hereinafter referred to by reference 3), respectively. The reference 1 discloses an apparatus and a method of utilizing memory cells as a low integration memory chip by bonding residual address signals to the ground GND or the power voltage VDD in case that any specific partial blocks in the memory cells are frequently failed. The reference 2 discloses an apparatus and a method by which a larger density semiconductor memory device can be converted to a smaller density semiconductor memory device by fixing one address bit to select xc2xd of 2n partial blocks. The reference 3 discloses a method and structure for recovering smaller density memories from larger density memories, the structure includes a logic determining circuit which comprised of a plurality of fuses and transistors between address pads and address buffers. The logic determining circuit allows signals applied to the address pads through a fusing means to be ignored and forces a logic state on the address buffer.
As described in the above, the references 1 and 3 discloses a memory cell repairing technique for fixing an address state selecting residual address to thereby convert a high density memory to a smaller density memory. However, the conventional memory cell repairing techniques as disclosed in the references 1 and 3 can repair only the memory cell fails which are concentrated on the specific regions of the memory cells as shown in FIG. 8 or FIG. 11, but cannot repair such failure type as that shown in FIGS. 9 and 10.
That is, the conventional memory cell repairing techniques are limited to only the specific memory cell failures as described above, not a variety of memory cell failures, thereby decreasing yield and function of good semiconductor memory devices, particularly decreasing productivity of the semiconductor memory devices.
The present invention is provided to solve the aforementioned problems and it is an object of the present invention to provide a semiconductor memory cell repairing apparatus and method therefore that can effectively repair memory cells although various types of failures in memory cells are generated.
It is another object of the present invention to provide a memory cell repairing apparatus and a method thereof that can selectively repair normal memory cells out of a variety of types of memory cell failures by converting address scramble map during recovery of smaller density memories from larger density memories due to memory cell failure, thereby increasing yield and productivity of good semiconductor memory devices.
In order to accomplish the aforementioned objects of the present invention, there is provided a memory cell repairing apparatus comprising: state fixing parts operable to fix a specific external input address signal out of external input addresses as a constant state, address input receivers operable to receive output signals of the state selecting part and external input signals, address code selecting part operable to receive output address signals of the address input receiver and to convert output address signal path through a control signal which selects address code change to output a changed address signal, and address input buffers operable to receive the changed address signal outputted from the address code selecting part to output a new internal address.
A method of repairing memory cells by using the memory cell repairing apparatus, comprises checking a failure rule through a bit map test of failed memory cells, fixing a residual address signal as a constant state to convert it to a smaller density when a failure rule in the failed memory cells is detected, converting an address scramble map to selectively convert an output-address-signal path by a predetermined control signal in response to the address signal input to thereby change an address code, and converting high density memory cells to smaller density memory cells by outputting the changed address code.
In accordance with the other aspect of the present invention, there is provided a memory cell repairing apparatus being applied to an on-chip cache memory comprising a micro processor for receiving a bit map address signal from the-cache memory to detect failure in memory cells and generating a residual address fixing control signal for a smaller density and a control signal for conversion of an address scramble map, an address code selecting part for changing an input-to-output address signal path to convert the residual address fixing control signal for a smaller density by the microprocessor and the address scramble map conversion in response to the control signal to thereby output the converted address buffer signal, and a cache memory being utilized as a smaller density memory cell when a converted address buffer signal is output after an address scramble conversion is performed to a smaller density by the address code selecting part.